AMD has announced the Versal Premium Series Gen 2, a new family of adaptive system-on-chips (SoCs) engineered to deliver unparalleled acceleration across a diverse range of workloads. These SoCs mark a significant leap forward in the FPGA industry, being the first to integrate Compute Express Link (CXL) 3.1, PCIe Gen6, and LPDDR5X memory support in hard IP.
This combination of cutting-edge interface and memory technologies enables rapid and efficient data movement between processors and accelerators. By leveraging CXL 3.1 and LPDDR5X, Versal Premium Gen 2 SoCs unlock greater memory resources with increased speed, addressing the escalating demands of data-intensive applications in data centers, communication networks, test and measurement systems, and aerospace and defense.
AMD’s commitment to open standards is evident in its support for CXL, an industry-standard interconnect designed to optimize communication between processors and accelerators. With the integration of CXL 3.1 and PCIe Gen6, Versal Premium Gen 2 devices achieve industry-leading host-to-accelerator bandwidth. PCIe Gen6 alone delivers a 2-4X increase in line rate compared to competing FPGAs, while CXL 3.1 over PCIe Gen6 doubles the bandwidth of devices using CXL 2.1 at comparable latencies.
Furthermore, when paired with AMD EPYC CPUs, Versal Premium Gen 2 SoCs create a high-performance synergy, enabling systems to tackle data-intensive workloads and manage rapid data growth with exceptional efficiency. CXL’s memory coherency capabilities further enhance this synergy, facilitating true heterogeneous computing.
Versal Premium Gen 2 SoCs feature the fastest LPDDR5X memory connectivity currently available, operating at speeds up to 8533 Mb/s. This translates to significantly faster data transfers and improved real-time responsiveness. Moreover, the integration of CXL memory expansion modules allows for scalable memory pooling and extension across multiple accelerators, optimizing memory utilization and maximizing bandwidth.
The ability to dynamically allocate memory pools enhances efficiency, particularly in multi-headed single logic device (MH-SLD) configurations, enabling operation without a fabric or switch while supporting up to two CXL hosts.
Security is a paramount concern, and Versal Premium Gen 2 SoCs incorporate advanced features to ensure data integrity and confidentiality. These SoCs are the first FPGAs to include integrated PCIe Integrity and Data Encryption (IDE) in hard IP. Inline encryption within the hard DDR memory controllers safeguards data at rest, while high-speed crypto engines secure data in transit at doubled line rates compared to previous generations.
Development tools for the AMD Versal Premium Series Gen 2 are anticipated in Q2 2025, with silicon samples following in early 2026. Production shipments are expected to commence in the second half of 2026.
